Antenna Effect

Antenna Effect

•Antenna effect occurs due to the charge that builds up on metal during fabrication.

•Antenna violation  is caused when the antenna ratio

•     (Exposed gate area/gate oxide area) exceeds the value mentioned in the PDK.
  •Ions will get collected on the exposed wafer during polysilicon/Metal etching. The remaining portion of the metal/PolySi, which is not getting etched act as an antenna to collect the ions injected during this Plasma processing
• •Antenna effect occurs during the dry etching(Reactive Ion Etching) step of fabrication process. This process is conducted in side a chamber , the wafer will be grounded during the process as shown in Fig1.
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• •This accumulated charges causes a potential, which when becomes large causes gate oxide damage, Vth shift etc making the chip useless.

  •Solutions

    -Can be avoided by using metal jumpers.

    -Can be avoided by using NAC (Net Area Check) diode.

    - Can be avoided by using dummy transistor which will increase the gate oxide area.      

  • •Using Jumpers:

    A shot jumper of higher metal is placed near the transistor that causes the antenna violation.

    Suppose Antenna violation is occurring in Nth metal  and we are using N-1 th  metal jumper, then this will again cause violation as N-1th metal will be already fabricated when nth metal is fabricated, so we must use N+1th metal as jumper.

      

   *Jumpers introduce extra vias and therefore  degrade both manufacturing yield and timing performance.                                 

  

  
  

  • •NAC diode

    Any diffusion connected to net causes the ions collected during antenna violation to reach the substrate as reverse leakage current before the occurrence of gate oxide damage. So we purposefully add a NAC(Net Area Check) diode near (as near as possible allowed in the PDK) the transistor causing violation.

    Make sure that the diode is reverse biased during normal operation of the circuit.

      Fig 4

  * NAC diode are only applicable for M1 and above not for poly(use jumpers), since diodes are made of diffusion, which will be formed in the wafer after polysilicon deposition step. So during poly etching there won’t be any diode for protection.
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• •Dummy transistor
    - Connect a dummy transistor in such a way that its Gate is connected to the antenna net causing violation and Source, Drain & Bulk connected to GND. This will increase the gate oxide area thereby reducing Antenna ratio.
    - Dummy transistors can also be connected as -diode with S & D connected to the Antenna net and Gate & bulk connected to the bulk potential.
        Fig 5
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For Cu process:

•Unlike aluminium, antenna effects in copper processes are far more dependent upon vias than on the metallization stages of processing.

  Due to Dual damascene process used in Cu.

•In the case of aluminium processing, the metal is deposited everywhere, and subsequently etched away to leave only the desired interconnect lines. This extensive etching produces significant charge accumulation proportional to the area (top) of the metal lines and to the perimeter (sides) of the metal lines

•Copper processing is far less susceptible, because it is the oxide that is trenched. During the trenching, there is no metal to accumulate a charge. These trenches are then filled, followed by some minor etching to remove excess metal.

•At this step, there is an opportunity for the copper metal regions to accumulate some charge. While the excess metal does extend beyond the trench itself, this charge can still largely be modeled as a proportion of the drawn metal layer’s surface area. Because this charge build-up is relatively small compared to the aluminium case, it is far less problematic.

• •After each metallization step, chemical-mechanical polishing (CMP) is applied. During the CMP process, the wafer (including all the metal applied to that point) is grounded. As a result, any remaining charge on the metal is removed. Damage to the transistor prior to the CMP stage, however, still remains.

•While the metallization manufacturing stages in copper is far less susceptible to the antenna affect than the aluminium process, there is another step that also introduces antenna charges—the via processing step

• •In this case, as the vias are trenched from the oxide, the lower-level metal is briefly exposed to the charge from the etch. This charge is proportional to the area of the vias on the metal line. Ironically, as we continue to add more vias to minimize void issues, CMP issues, or mask alignment issues, we are at the same time adding more charge, and potentially putting more transistors at risk of failure due to the antenna effects. In the case of copper, charge build-up due to vias is typically greater than the charge at the actual metal stage, and, as a result, is usually the largest contributor to antenna failures.

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Thank You

Latchup

     Latchup ( Fig 1 & 2 )

•Latchup is the creation of low impedance path between power supply rails because of the triggering of the parasitic BJT’s present in CMOS structure.

•If source of NMOS is pulled below ground , it will inject minority carriers electrons (with respect to substrate) into the  substrate ( base of the BJT), turning ON Qn transistor.

•The collector of Qn is the base of Qp so it will turn on Qp also. Thus each BJTs supplies the other BJT base current. Thus it will become self sustaining if β1 β2 > 1.

•The circuit will remain in this state unless power is removed. This structure conduct so much current that it overheats and destruct the IC.

Solution (Fig 3-6)

•All solutions are based on reducing the beta of transistors and reducing the substrate / Nwell resistance values.

  1) Increase the spacing between transistors, it will increase the IB, thereby reducing β(IC/IB) of transistors.

  2) Next is reducing substrate and Nwell resistance by providing substrate tie (P-tap connected to VSS for NMOS) / Nwell tie respectively ( N-tap connected to VDD for PMOS) in a ring shape, which is the body connection of the transistors. This structure should be placed as near to the device as permitted by DRC rules.

    Eg: Ring type ptap consists of P-type diffusion + full contacts connected by using metal 1, this structure causes the substrate R in parallel thereby reducing the effective Rsubstarte. Similar is the case of N-tap which reduces Rnwell.

•Next is to provide an alternate collector current path so that it won’t turn on the other BJT structure. This is done by providing a Guardring which is of the opposite type of body contact ie, for an NMOS it’s an Ntap connected to VDD and for PMOS it’s a Ptap outside Nwell connected to VSS. This structure should be placed outside Nwell for PMOS and for NMOS as permitted by DRC rules.

Thank You.