Latchup

     Latchup ( Fig 1 & 2 )

•Latchup is the creation of low impedance path between power supply rails because of the triggering of the parasitic BJT’s present in CMOS structure.

•If source of NMOS is pulled below ground , it will inject minority carriers electrons (with respect to substrate) into the  substrate ( base of the BJT), turning ON Qn transistor.

•The collector of Qn is the base of Qp so it will turn on Qp also. Thus each BJTs supplies the other BJT base current. Thus it will become self sustaining if β1 β2 > 1.

•The circuit will remain in this state unless power is removed. This structure conduct so much current that it overheats and destruct the IC.

Solution (Fig 3-6)

•All solutions are based on reducing the beta of transistors and reducing the substrate / Nwell resistance values.

  1) Increase the spacing between transistors, it will increase the IB, thereby reducing β(IC/IB) of transistors.

  2) Next is reducing substrate and Nwell resistance by providing substrate tie (P-tap connected to VSS for NMOS) / Nwell tie respectively ( N-tap connected to VDD for PMOS) in a ring shape, which is the body connection of the transistors. This structure should be placed as near to the device as permitted by DRC rules.

    Eg: Ring type ptap consists of P-type diffusion + full contacts connected by using metal 1, this structure causes the substrate R in parallel thereby reducing the effective Rsubstarte. Similar is the case of N-tap which reduces Rnwell.

•Next is to provide an alternate collector current path so that it won’t turn on the other BJT structure. This is done by providing a Guardring which is of the opposite type of body contact ie, for an NMOS it’s an Ntap connected to VDD and for PMOS it’s a Ptap outside Nwell connected to VSS. This structure should be placed outside Nwell for PMOS and for NMOS as permitted by DRC rules.

Thank You.